De-pop on-device decoupling for bga

ABSTRACT

Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation application of U.S. application Ser. No.13/231,609 filed Sep. 13, 2011, which is hereby incorporated byreference for all purposes as if fully set forth herein.

FIELD OF THE INVENTION

The invention is directed to Ball Grid Array (BGA) packages for use onelectronic circuit cards and more specifically, improved decouplingarrangements.

BACKGROUND OF THE INVENTION

As electronic integrated circuit (EIC) packages such as Ball Grid Array(BGA) packages increase in density, in interface connection density, andin clock speed, the requirements for electrically decoupling a BGAdevice become more stringent. It is advantageous to place these couplingcapacitors as close to the BGA pads as possible. Typical placement ofsurface-mount decoupling capacitors is adjacent to the BGA device on thesame side of the electronic circuit board (printed circuit board or PCB)or on the opposite side of the electronic circuit board, connected byvias through the circuit board. Both of these techniques can introduceparasitic inductance due to the length of the vias and/or the routingleads.

Therefore, improvement to decoupling techniques for BGA devices ishighly desirable.

SUMMARY OF THE INVENTION

Embodiments of the invention place surface-mount devices such asdecoupling capacitors, resistors or other devices directly on theunderside of a ball grid array (BGA) electronic integrated circuit (EIC)package, in place of de-populated BGA pads.

Some embodiments of the invention provide an electronic integratedcircuit (EIC) package comprising: an EIC substrate; an array of ballgrid array (BGA) pads on a first side of the EIC substrate, arranged ina grid pattern of rows and columns; and contact pads on the first sideof the EIC substrate to accommodate electrical connection of asurface-mount device, wherein the surface-mount device occupies a gridlocation of the grid pattern in place of one or more BGA pads.

In some embodiments the contact pads comprise at least two adjacentcontact pads.

In some embodiments the contact pad is connected to an adjacent BGA padby a conductor on the first side of the EIC substrate.

In some embodiments the surface-mount device comprises a two-portdevice.

In some embodiments the surface-mount device comprises a decouplingcapacitor.

In some embodiments the surface-mount device is selected from the setof: capacitor, resistor, inductor, diode, transistor, capacitor array,and resistor-capacitor circuit.

In some embodiments the BGA grid comprises a pitch of between about 0.4mm×0.4 mm and about 1.27 mm×1.27 mm.

In some embodiments the BGA grid comprises an irregular pitch.

Other embodiments of the invention provide a computer-aided design toolfor accommodating a surface-mount device on a first surface of a ballgrid array (BGA) electronic integrated circuit (EIC) package, the toolcomprising: a design tool mode to identify, in an EIC configuration ofBGA pads in a grid pattern on the first side of the EIC package, atleast two contact pads for forming directly on the first surface, thecontact pads for direct mounting of and connection to the surface-mountdevice, wherein the surface-mount device occupies a grid location of thegrid pattern in place of one or more BGA pads.

BRIEF DESCRIPTION OF THE DRAWINGS

Some embodiments of apparatus and/or methods in accordance withembodiments of the present invention are now described, by way ofexample only, and with reference to the accompanying drawings in which:

FIG. 1 illustrates a layout of surface mount devices within a BGA gridaccording to embodiments of the invention

FIG. 2 illustrates a layout of surface mount devices within a BGA gridon an EIC substrate according to other embodiments of the invention;

FIG. 3A illustrates placement of surface mount devices on an EICsubstrate according to an embodiment of the invention;

FIG. 3B illustrates placement of surface mount devices between BGAsolder balls on an EIC substrate according to an embodiment of theinvention; and

FIG. 3C illustrates placement of an EIC device on a printed circuitboard according to an embodiment of the invention.

In the figures, like features are denoted by like reference characters.

DETAILED DESCRIPTION

FIG. 1 illustrates a bottom surface layout of an electronic integratedcircuit (EIC) package having BGA pads 102 arranged in a BGA grid pitchof 0.80 mm×0.80 mm. Certain BGA pads (105, 109, 115, 117) arede-populated and the resulting free space is used for placingsurface-mount decoupling capacitors 104, 106, 108, 110, 112, 114, and116. By depopulating BGA pad 105, there is room to mount a ‘0402’package surface-mount capacitor 104. In a similar manner, BGA pad 109 isde-populated to provide room for two ‘0201’ package surface-mountcapacitors 106, 108. BGA pad 115 is de-populated to provide room forthree ‘01005’ package surface-mount capacitors 110, 112, 114. BGA pad117 is de-populated to provide room for capacitor array 116 in astandard ‘0302’ surface-mount package (0.030″×0.020″). The surface-mountdevices can be placed in a variety of orientations includinglongitudinally, laterally or diagonally with respect to the BGA grid.

FIG. 2 illustrates a bottom surface layout of an electronic integratedcircuit (EIC) package having BGA pads 202 arranged in a BGA grid pitchof 1.00 mm×1.00 mm. BGA pad 207 is de-populated and the resulting freespace is used for placing two ‘0201’ package surface-mount decouplingcapacitors 204, 206. BGA pad 209 is similarly de-populated and theresulting free space is used for placing a ‘0402’ package surface-mountdecoupling capacitor 209. BGA pad 211 is de-populated to provide roomfor capacitor array 210 in a standard ‘0302’ surface-mount package andBGA pad 215 is de-populated to provide room for placing three ‘01005’package surface-mount decoupling capacitors 212, 213, and 214.

Many BGA EIC packages do not use the full array of BGA pads which canprovide the flexibility to use the space for surface-mount components.This can be especially advantageous for devices such as decouplingcapacitors which benefit from mounting in close proximity to BGA padsfor voltage supply connections and ground connections on BGA EICpackages to minimize parasitic inductance. As the trend toward using BGAgrid patterns with smaller pitches continues, such as 1.27 mm×1.27 mm,1.0 mm×1.0 mm, 0.8 mm×0.8 mm, and 0.5 mm×0.5 mm there is less spaceavailable between BGA pads in a full BGA grid pattern for mountingsurface-mount components such as standard ‘0402’ surface-mount package(0.04″×0.02″), ‘0201’ package (0.020″×0.010″) or ‘01005’ package(0.010″×0.005″). Embodiments of this invention advantageously providefor locating surface mount components in place of BGA pads at ball gridarray locations. Embodiments of the invention are suited as well for BGApackages having an irregular pitch where longitudinal rows have adifferent pitch than lateral rows such as for example 0.8 mm×1.0 mm

Other embodiments contemplated by this invention include depopulating aplurality of BGA pads on a BGA EIC package in order to accommodatesurface-mount devices between the remaining BGA pads.

Additional embodiments of this invention contemplate the use ofsurface-mount devices including two-port devices such as capacitors,resistors, diodes, inductors, etc. as well as multi-port devices such ascapacitor arrays, resistor-capacitor combinations, as well as activedevices such as transistors.

FIGS. 3A, 3B, 3C illustrate placement of surface-mount devices on an EICsubstrate 302 relative to BGA solder spheres 314 and an electronicprinted circuit board 318. The EIC has a substrate 302 and cover orovermold 304 to protect the integrated circuit. On a first surface 303of substrate 302, are BGA pads 306 arranged in a grid pattern. BGA pad307 is de-populated, that is, if the BGA grid pattern were full, therewould be a BGA pad at location 307. By not populating BGA pad 307, thereis space to accommodate surface-mount device 310. Contact pads 308 canbe connected to adjacent BGA pads 306 to minimize connection distancebetween device 310 and the circuitry of BGA EIC 302 as discussedpreviously.

During assembly, surface-mount component 310 is placed on surface-mountpads 308 which have been previously prepared with solder paste 311.Surface-mount device 310 can be held in position with the tacky solderpaste 311 on the surface mount pads and optionally by adhesive 313between the body of device 310 and the surface 303. Additional surfacemount devices are handled similarly to device 310. BGA solder balls(spheres) 314 are applied onto BGA pads 306. The balls 314 can be heldin place by tacky flux as is well known in the art. The EIC packageassembly 315 with surface mount devices 310, 312 and solder balls 314 isthen reflow-soldered to form an electrical and mechanical bond betweensurface-mount device 310 and pads 308 and between BGA solder balls 314and BGA pads 306. Solder paste 311 reflows to form solder fillets 316.

EIC package assembly 319 with solder balls 314 and with surface-mountdevice 310 can then be operationally tested as a unit to verifyoperation of the EIC in conjunction with device 310. Devices 310, 312and solder fillets 316, 317 can also be easily visually inspected atthis stage. Advantageously, it is easier to address any problems withthe surface-mount components 310, 312 then after the EIC is mounted on aprinted circuit board. These steps can be performed by the manufacturerof the EIC assembly prior to delivery to a customer who would mount theEIC assembly on an electronic printed circuit board.

With reference to FIG. 3C, assembly 319 can then be mounted on printedcircuit board 318 and reflow soldered to bond solder balls 314 to BGAsolder pads 320. Note that it is possible to mount EIC package assembly319 with surface-mount component 310 over top of unused BGA pad 321 onprinted circuit board 318. In this manner, EIC package designs havingunused BGA pads (no connection) could be redesigned to accommodatesurface-mount devices occupying the location of an unused BGA pad 307.Such a modified design could be used with a printed circuit board wherethe corresponding no-connection BGA pad 321 is still present. Otherwise,future EIC packages can be designed to optimize the location ofdecoupling capacitors between voltage source connections and groundconnections and printed circuit boards can be designed accordingly.

The description and drawings merely illustrate the principles of theinvention. It will thus be appreciated that those skilled in the artwill be able to devise various arrangements that, although notexplicitly described or shown herein, embody the principles of theinvention and are included within its spirit and scope. Furthermore, allexamples recited herein are principally intended expressly to be onlyfor pedagogical purposes to aid the reader in understanding theprinciples of the invention and the concepts contributed by theinventor(s) to furthering the art, and are to be construed as beingwithout limitation to such specifically recited examples and conditions.Moreover, all statements herein reciting principles, aspects, andembodiments of the invention, as well as specific examples thereof, areintended to encompass equivalents thereof.

It should be appreciated by those skilled in the art that any blockdiagrams herein represent conceptual views of illustrative circuitryembodying the principles of the invention. Numerous modifications,variations and adaptations may be made to the embodiment of theinvention described above without departing from the scope of theinvention, which is defined in the claims.

What is claimed is:
 1. An electronic integrated circuit (EIC) packagecomprising: an EIC substrate; an array of ball grid array (BGA) pads ona first side of said EIC substrate, arranged in a grid pattern of rowsand columns; and contact pads on said first side of said EIC substrateto accommodate electrical connection of a surface-mount device, whereinsaid surface-mount device occupies a grid location of said grid patternin place of one or more BGA pads.
 2. The EIC package of claim 1, whereinsaid contact pads comprise at least two adjacent contact pads.
 3. TheEIC package of claim 2, wherein each of the contact pads is connected toan adjacent BGA pad by a conductor on said first side of said EICsubstrate.
 4. The EIC package of claim 1, wherein said surface-mountdevice comprises a two-port device.
 5. The EIC package of claim 4,wherein said surface-mount device comprises a decoupling capacitor. 6.The EIC package of claim 1, wherein said surface-mount device isselected from a set of a capacitor, a resistor, an inductor, a diode, atransistor, a capacitor array, and a resistor-capacitor circuit.
 7. TheEIC package of claim 1, wherein said BGA grid comprises a pitch ofbetween about 0.4 mm×0.4 mm and about 1.27 mm×1.27 mm.
 8. The EICpackage of claim 7, wherein said BGA grid comprises an irregular pitch.9. A computer-aided design tool for accommodating a surface-mount deviceon a first surface of a ball grid array (BGA) electronic integratedcircuit (EIC) package, said tool comprising: a design tool configured toidentify, in an EIC configuration of BGA pads in a grid pattern on saidfirst side of said EIC package, at least two contact pads for formingdirectly on said first surface, said contact pads for direct mounting ofand connection to said surface-mount device, wherein said surface-mountdevice occupies a grid location of said grid pattern in place of one ormore BGA pads.
 10. The computer-aided design tool of claim 9, whereineach of the contact pads is connected to an adjacent BGA pad by aconductor on said first side of said EIC package.
 11. The computer-aideddesign tool of claim 9, wherein said surface-mount device comprises atwo-port device.
 12. The computer-aided design tool of claim 11, whereinsaid surface-mount device comprises a decoupling capacitor.
 13. Thecomputer-aided design tool of claim 9, wherein said surface-mount deviceis selected from a set of a capacitor, a resistor, an inductor, a diode,a transistor, a capacitor array, and a resistor-capacitor circuit. 14.The computer-aided design tool of claim 9, wherein said BGA gridcomprises a pitch of between about 0.4 mm×0.4 mm and about 1.27 mm×1.27mm.
 15. The computer-aided design tool of claim 14, wherein said BGAgrid comprises an irregular pitch.
 16. The EIC package of claim 1,wherein the surface-mount device is placed diagonally with respect tothe grid pattern.
 17. The computer-aided design tool of claim 9, whereinthe surface-mount device is placed diagonally with respect to the gridpattern.